/***************************************************************************//**
* \file cyip_mixer.h
*
* \brief
* MIXER IP definitions
*
********************************************************************************
* \copyright
* (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#ifndef _CYIP_MIXER_H_
#define _CYIP_MIXER_H_

#include "cyip_headers.h"

/*******************************************************************************
*                                    MIXER
*******************************************************************************/

#define MIXER_MIXER_SRC_STRUCT_SECTION_SIZE     0x00000100UL
#define MIXER_MIXER_DST_STRUCT_SECTION_SIZE     0x00000100UL
#define MIXER_MIXER_TX_STRUCT_SECTION_SIZE      0x00000100UL
#define MIXER_SECTION_SIZE                      0x00010000UL

/**
  * \brief Mixer source structure (MIXER_MIXER_SRC_STRUCT)
  */
typedef struct {
  __IOM uint32_t SRC_CTL;                       /*!< 0x00000000 Source control */
   __IM uint32_t SRC_STATUS;                    /*!< 0x00000004 Source status */
   __IM uint32_t RESERVED[3];
  __IOM uint32_t SRC_FADE_CTL;                  /*!< 0x00000014 Source fade control */
   __IM uint32_t SRC_FADE_STATUS;               /*!< 0x00000018 Source fade status */
  __IOM uint32_t SRC_FADE_CMD;                  /*!< 0x0000001C Source fade command */
  __IOM uint32_t SRC_GAIN_CTL;                  /*!< 0x00000020 Source gain control */
   __IM uint32_t RESERVED1[23];
  __IOM uint32_t SRC_FIFO_CTL;                  /*!< 0x00000080 Source FIFO control */
   __IM uint32_t SRC_FIFO_STATUS;               /*!< 0x00000084 Source FIFO status */
   __OM uint32_t SRC_FIFO_WR;                   /*!< 0x00000088 Source FIFO write */
   __IM uint32_t RESERVED2[13];
  __IOM uint32_t INTR_SRC;                      /*!< 0x000000C0 Interrupt */
  __IOM uint32_t INTR_SRC_SET;                  /*!< 0x000000C4 Interrupt set */
  __IOM uint32_t INTR_SRC_MASK;                 /*!< 0x000000C8 Interrupt mask */
   __IM uint32_t INTR_SRC_MASKED;               /*!< 0x000000CC Interrupt masked */
   __IM uint32_t RESERVED3[12];
} MIXER_MIXER_SRC_STRUCT_Type;                  /*!< Size = 256 (0x100) */

/**
  * \brief Mixer destination structure (MIXER_MIXER_DST_STRUCT)
  */
typedef struct {
  __IOM uint32_t DST_CTL;                       /*!< 0x00000000 Destination control */
   __IM uint32_t RESERVED[4];
  __IOM uint32_t DST_FADE_CTL;                  /*!< 0x00000014 Destination fade control */
   __IM uint32_t DST_FADE_STATUS;               /*!< 0x00000018 Destination fade status */
  __IOM uint32_t DST_FADE_CMD;                  /*!< 0x0000001C Destination fade command */
  __IOM uint32_t DST_GAIN_CTL;                  /*!< 0x00000020 Destination gain control */
   __IM uint32_t RESERVED1[23];
  __IOM uint32_t DST_FIFO_CTL;                  /*!< 0x00000080 Destination FIFO control */
   __IM uint32_t DST_FIFO_STATUS;               /*!< 0x00000084 Destination FIFO status */
   __IM uint32_t DST_FIFO_RD;                   /*!< 0x00000088 Destination FIFO read */
   __IM uint32_t DST_FIFO_RD_SILENT;            /*!< 0x0000008C Destination FIFO silent read */
   __IM uint32_t RESERVED2[12];
  __IOM uint32_t INTR_DST;                      /*!< 0x000000C0 Interrupt */
  __IOM uint32_t INTR_DST_SET;                  /*!< 0x000000C4 Interrupt set */
  __IOM uint32_t INTR_DST_MASK;                 /*!< 0x000000C8 Interrupt mask */
   __IM uint32_t INTR_DST_MASKED;               /*!< 0x000000CC Interrupt masked */
   __IM uint32_t RESERVED3[12];
} MIXER_MIXER_DST_STRUCT_Type;                  /*!< Size = 256 (0x100) */

/**
  * \brief Mixer TX structure (MIXER_MIXER_TX_STRUCT)
  */
typedef struct {
  __IOM uint32_t TX_CTL;                        /*!< 0x00000000 TX control */
   __IM uint32_t RESERVED[3];
  __IOM uint32_t TX_IF_CTL;                     /*!< 0x00000010 TX interface control */
   __IM uint32_t RESERVED1[27];
  __IOM uint32_t TX_FIFO_CTL;                   /*!< 0x00000080 TX FIFO control */
   __IM uint32_t RESERVED2[15];
  __IOM uint32_t INTR_TX;                       /*!< 0x000000C0 Interrupt */
  __IOM uint32_t INTR_TX_SET;                   /*!< 0x000000C4 Interrupt set */
  __IOM uint32_t INTR_TX_MASK;                  /*!< 0x000000C8 Interrupt mask */
   __IM uint32_t INTR_TX_MASKED;                /*!< 0x000000CC Interrupt masked */
   __IM uint32_t RESERVED3[12];
} MIXER_MIXER_TX_STRUCT_Type;                   /*!< Size = 256 (0x100) */

/**
  * \brief MIXER (MIXER)
  */
typedef struct {
   __IM uint32_t RESERVED[8192];
        MIXER_MIXER_SRC_STRUCT_Type MIXER_SRC_STRUCT[8]; /*!< 0x00008000 Mixer source structure */
   __IM uint32_t RESERVED1[3584];
        MIXER_MIXER_DST_STRUCT_Type MIXER_DST_STRUCT; /*!< 0x0000C000 Mixer destination structure */
   __IM uint32_t RESERVED2[960];
        MIXER_MIXER_TX_STRUCT_Type MIXER_TX_STRUCT; /*!< 0x0000D000 Mixer TX structure */
} MIXER_Type;                                   /*!< Size = 53504 (0xD100) */


/* MIXER_MIXER_SRC_STRUCT.SRC_CTL */
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_FS_RATIO_Pos 12UL
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_FS_RATIO_Msk 0x7000UL
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_CH0_SEL_Pos 16UL
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_CH0_SEL_Msk 0x30000UL
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_CH1_SEL_Pos 18UL
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_CH1_SEL_Msk 0xC0000UL
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_ENABLED_Pos 31UL
#define MIXER_MIXER_SRC_STRUCT_SRC_CTL_ENABLED_Msk 0x80000000UL
/* MIXER_MIXER_SRC_STRUCT.SRC_STATUS */
#define MIXER_MIXER_SRC_STRUCT_SRC_STATUS_PHASE_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_SRC_STATUS_PHASE_Msk 0xFUL
/* MIXER_MIXER_SRC_STRUCT.SRC_FADE_CTL */
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CTL_CODE_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CTL_CODE_Msk 0x7FUL
/* MIXER_MIXER_SRC_STRUCT.SRC_FADE_STATUS */
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_STATUS_PACE_Pos 16UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_STATUS_PACE_Msk 0x3FF0000UL
/* MIXER_MIXER_SRC_STRUCT.SRC_FADE_CMD */
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_FADE_IN_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_FADE_IN_Msk 0x1UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_FADE_OUT_Pos 1UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_FADE_OUT_Msk 0x2UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_AUTO_DEACTIVATE_Pos 8UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_AUTO_DEACTIVATE_Msk 0x100UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_PACE_Pos 16UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FADE_CMD_PACE_Msk 0x3FF0000UL
/* MIXER_MIXER_SRC_STRUCT.SRC_GAIN_CTL */
#define MIXER_MIXER_SRC_STRUCT_SRC_GAIN_CTL_CODE_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_SRC_GAIN_CTL_CODE_Msk 0x7FUL
/* MIXER_MIXER_SRC_STRUCT.SRC_FIFO_CTL */
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7FUL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_CTL_MUTE_Pos 16UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_CTL_MUTE_Msk 0x10000UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_CTL_ACTIVE_Pos 18UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_CTL_ACTIVE_Msk 0x40000UL
/* MIXER_MIXER_SRC_STRUCT.SRC_FIFO_STATUS */
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_STATUS_USED_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_STATUS_USED_Msk 0xFFUL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_STATUS_RD_PTR_Pos 16UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_STATUS_RD_PTR_Msk 0x7F0000UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_STATUS_WR_PTR_Pos 24UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_STATUS_WR_PTR_Msk 0x7F000000UL
/* MIXER_MIXER_SRC_STRUCT.SRC_FIFO_WR */
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_WR_DATA_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_SRC_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
/* MIXER_MIXER_SRC_STRUCT.INTR_SRC */
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_FIFO_OVERFLOW_Pos 1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_FIFO_OVERFLOW_Msk 0x2UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_FADED_OUT_Pos 8UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_FADED_OUT_Msk 0x100UL
/* MIXER_MIXER_SRC_STRUCT.INTR_SRC_SET */
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_SET_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_SET_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_SET_FIFO_OVERFLOW_Pos 1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_SET_FIFO_OVERFLOW_Msk 0x2UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_SET_FADED_OUT_Pos 8UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_SET_FADED_OUT_Msk 0x100UL
/* MIXER_MIXER_SRC_STRUCT.INTR_SRC_MASK */
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASK_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASK_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASK_FIFO_OVERFLOW_Pos 1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASK_FIFO_OVERFLOW_Msk 0x2UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASK_FADED_OUT_Pos 8UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASK_FADED_OUT_Msk 0x100UL
/* MIXER_MIXER_SRC_STRUCT.INTR_SRC_MASKED */
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASKED_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASKED_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASKED_FIFO_OVERFLOW_Pos 1UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASKED_FIFO_OVERFLOW_Msk 0x2UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASKED_FADED_OUT_Pos 8UL
#define MIXER_MIXER_SRC_STRUCT_INTR_SRC_MASKED_FADED_OUT_Msk 0x100UL


/* MIXER_MIXER_DST_STRUCT.DST_CTL */
#define MIXER_MIXER_DST_STRUCT_DST_CTL_ENABLED_Pos 31UL
#define MIXER_MIXER_DST_STRUCT_DST_CTL_ENABLED_Msk 0x80000000UL
/* MIXER_MIXER_DST_STRUCT.DST_FADE_CTL */
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CTL_CODE_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CTL_CODE_Msk 0x7FUL
/* MIXER_MIXER_DST_STRUCT.DST_FADE_STATUS */
#define MIXER_MIXER_DST_STRUCT_DST_FADE_STATUS_PACE_Pos 16UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_STATUS_PACE_Msk 0x3FF0000UL
/* MIXER_MIXER_DST_STRUCT.DST_FADE_CMD */
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_FADE_IN_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_FADE_IN_Msk 0x1UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_FADE_OUT_Pos 1UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_FADE_OUT_Msk 0x2UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_AUTO_DEACTIVATE_Pos 8UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_AUTO_DEACTIVATE_Msk 0x100UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_PACE_Pos 16UL
#define MIXER_MIXER_DST_STRUCT_DST_FADE_CMD_PACE_Msk 0x3FF0000UL
/* MIXER_MIXER_DST_STRUCT.DST_GAIN_CTL */
#define MIXER_MIXER_DST_STRUCT_DST_GAIN_CTL_CODE_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_DST_GAIN_CTL_CODE_Msk 0x7FUL
/* MIXER_MIXER_DST_STRUCT.DST_FIFO_CTL */
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_CTL_TRIGGER_LEVEL_Msk 0x3FUL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_CTL_MUTE_Pos 16UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_CTL_MUTE_Msk 0x10000UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_CTL_ACTIVE_Pos 18UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_CTL_ACTIVE_Msk 0x40000UL
/* MIXER_MIXER_DST_STRUCT.DST_FIFO_STATUS */
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_STATUS_USED_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_STATUS_USED_Msk 0x7FUL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_STATUS_RD_PTR_Pos 16UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_STATUS_RD_PTR_Msk 0x3F0000UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_STATUS_WR_PTR_Pos 24UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_STATUS_WR_PTR_Msk 0x3F000000UL
/* MIXER_MIXER_DST_STRUCT.DST_FIFO_RD */
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_RD_DATA_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
/* MIXER_MIXER_DST_STRUCT.DST_FIFO_RD_SILENT */
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_RD_SILENT_DATA_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_DST_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
/* MIXER_MIXER_DST_STRUCT.INTR_DST */
#define MIXER_MIXER_DST_STRUCT_INTR_DST_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_FADED_OUT_Pos 8UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_FADED_OUT_Msk 0x100UL
/* MIXER_MIXER_DST_STRUCT.INTR_DST_SET */
#define MIXER_MIXER_DST_STRUCT_INTR_DST_SET_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_SET_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_SET_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_SET_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_SET_FADED_OUT_Pos 8UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_SET_FADED_OUT_Msk 0x100UL
/* MIXER_MIXER_DST_STRUCT.INTR_DST_MASK */
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASK_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASK_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASK_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASK_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASK_FADED_OUT_Pos 8UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASK_FADED_OUT_Msk 0x100UL
/* MIXER_MIXER_DST_STRUCT.INTR_DST_MASKED */
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASKED_FIFO_TRIGGER_Pos 0UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASKED_FIFO_TRIGGER_Msk 0x1UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASKED_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASKED_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASKED_FADED_OUT_Pos 8UL
#define MIXER_MIXER_DST_STRUCT_INTR_DST_MASKED_FADED_OUT_Msk 0x100UL


/* MIXER_MIXER_TX_STRUCT.TX_CTL */
#define MIXER_MIXER_TX_STRUCT_TX_CTL_WORD_SIZE_Pos 0UL
#define MIXER_MIXER_TX_STRUCT_TX_CTL_WORD_SIZE_Msk 0xFUL
#define MIXER_MIXER_TX_STRUCT_TX_CTL_FORMAT_Pos 12UL
#define MIXER_MIXER_TX_STRUCT_TX_CTL_FORMAT_Msk 0x3000UL
#define MIXER_MIXER_TX_STRUCT_TX_CTL_MS_Pos     16UL
#define MIXER_MIXER_TX_STRUCT_TX_CTL_MS_Msk     0x10000UL
#define MIXER_MIXER_TX_STRUCT_TX_CTL_ENABLED_Pos 31UL
#define MIXER_MIXER_TX_STRUCT_TX_CTL_ENABLED_Msk 0x80000000UL
/* MIXER_MIXER_TX_STRUCT.TX_IF_CTL */
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CLOCK_DIV_Pos 0UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CLOCK_DIV_Msk 0xFFUL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CLOCK_SEL_Pos 8UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CLOCK_SEL_Msk 0x700UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_SCK_POLARITY_Pos 12UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_SCK_POLARITY_Msk 0x1000UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_WS_POLARITY_Pos 13UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_WS_POLARITY_Msk 0x2000UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CH0_EN_Pos 16UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CH0_EN_Msk 0x10000UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CH1_EN_Pos 17UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CH1_EN_Msk 0x20000UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CH_SIZE_Pos 24UL
#define MIXER_MIXER_TX_STRUCT_TX_IF_CTL_CH_SIZE_Msk 0x1F000000UL
/* MIXER_MIXER_TX_STRUCT.TX_FIFO_CTL */
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_MUTE_Pos 16UL
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_MUTE_Msk 0x10000UL
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_FREEZE_Pos 17UL
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_FREEZE_Msk 0x20000UL
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_ACTIVE_Pos 18UL
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_ACTIVE_Msk 0x40000UL
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_REPLAY_Pos 19UL
#define MIXER_MIXER_TX_STRUCT_TX_FIFO_CTL_REPLAY_Msk 0x80000UL
/* MIXER_MIXER_TX_STRUCT.INTR_TX */
#define MIXER_MIXER_TX_STRUCT_INTR_TX_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_IF_UNDERFLOW_Pos 8UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_IF_UNDERFLOW_Msk 0x100UL
/* MIXER_MIXER_TX_STRUCT.INTR_TX_SET */
#define MIXER_MIXER_TX_STRUCT_INTR_TX_SET_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_SET_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_SET_IF_UNDERFLOW_Pos 8UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_SET_IF_UNDERFLOW_Msk 0x100UL
/* MIXER_MIXER_TX_STRUCT.INTR_TX_MASK */
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASK_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASK_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASK_IF_UNDERFLOW_Pos 8UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASK_IF_UNDERFLOW_Msk 0x100UL
/* MIXER_MIXER_TX_STRUCT.INTR_TX_MASKED */
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASKED_FIFO_UNDERFLOW_Pos 2UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASKED_FIFO_UNDERFLOW_Msk 0x4UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASKED_IF_UNDERFLOW_Pos 8UL
#define MIXER_MIXER_TX_STRUCT_INTR_TX_MASKED_IF_UNDERFLOW_Msk 0x100UL


#endif /* _CYIP_MIXER_H_ */


/* [] END OF FILE */
